Tesi Robotica Un coprocessore per Stereo-Matching: Profiling ... | Page 82

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“MF_Tesi” — 2011/9/12 — 11:39 — page 82 — #82

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6.4. SINTESI DELL’ALGORITMO SU FPGA

Top-level Entity Name
Family
Device
Total logic elements
Total combinational functions
Dedicated logic registers
Total registers
Total pins
Total memory bits

82

mkTop
Cyclone IV GX
EP4CGX50CF23C6
6,341 / 49,888 ( 13 % )
6,295 / 49,888 ( 13 % )
976 / 49,888 ( 2 % )
976
93 / 307 ( 30 % )
1,829,653 / 2,562,048 ( 71 % )

Tabella 6.2: Riassunto della sintesi. Dimensioni immagine:
Processors su Cyclone IV GX EP4CGX50CF23C6

Top-level Entity Name
Family
Device
Total logic elements
Total combinational functions
Dedicated logic registers
Total registers
Total pins
Total memory bits

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160x120, 2

mkTop
Cyclone IV GX
EP4CGX75CF23C6
26,117 / 73,920 ( 35 % )
25,691 / 73,920 ( 35 % )
5,575 / 73,920 ( 8 % )
5575
85 / 307 ( 28 % )
2,380,610 / 4,257,792 ( 56 % )

Tabella 6.3: Riassunto della sintesi. Dimensioni immagine: 64x64, 16 Processors
su Cyclone IV GX EP4CGX75CF23C6

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