Tesi Robotica Algoritmi ed architetture per la risoluzione di... | Page 133

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input [(widthad_a-1):0] address_a;
input [(widthad_b-1):0] address_b;
input wren_a;
input wren_b;
input [(width_a-1):0] data_a;
input [(width_b-1):0] data_b;
output [(width_a-1):0] q_a;
output [(width_b-1):0] q_b;
input [width_be_a-1:0] byteena_a;
input [width_be_b-1:0] byteena_b;
reg clk_wire;

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altsyncram altsyncram_component (
.clock0 (clk_wire),
.clock1 (1’d1),
.clocken0 (1’d1),
.clocken1 (1’d1),
.clocken2 (1’d1),
.clocken3 (1’d1),
.aclr0 (1’d0),
.aclr1 (1’d0),
.addressstall_a (1’d0),
.addressstall_b (1’d0),
.eccstatus (),
.address_a (address_a),
.address_b (address_b),
.wren_a (wren_a),
.wren_b (wren_b),
.rden_a (1’d1),
.rden_b (1’d1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.byteena_a (byteena_a),
.byteena_b (byteena_b)
);
defparam
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",