Tesi Robotica Algoritmi ed architetture per la risoluzione di... | Page 134

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altsyncram_component.init_file = init_file,
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.numwords_a = numwords_a,
altsyncram_component.numwords_b = numwords_b,
altsyncram_component.widthad_a = widthad_a,
altsyncram_component.widthad_b = widthad_b,
altsyncram_component.width_a = width_a,
altsyncram_component.width_b = width_b,
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.width_byteena_a = width_be_a,
altsyncram_component.width_byteena_b = width_be_b;
always @(*) begin
clk_wire = clk;
end
endmodule
module de2 (CLOCK_50, KEY, SW, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6,
HEX7, LEDG);
input CLOCK_50;
output [7:0] LEDG;
input [1:0] KEY;
input [15:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
wire clk;
wire reset = ~KEY[0];