Tesi Robotica Algoritmi ed architetture per la risoluzione di... | Page 131

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end

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endmodule
‘timescale 1 ns / 1 ns
module main
(
clk,
clk2x,
clk1x_follower,
reset,
start,
finish,
return_val,
memory_controller_enable_a,
memory_controller_address_a,
memory_controller_write_enable_a,
memory_controller_in_a,
memory_controller_size_a,
memory_controller_out_a,
memory_controller_enable_b,
memory_controller_address_b,
memory_controller_write_enable_b,
memory_controller_in_b,
memory_controller_size_b,
memory_controller_out_b,
memory_controller_waitrequest
);

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input clk;
input clk2x;
input clk1x_follower;
input reset;
input start;
output reg finish;
output reg [31:0] return_val;
output reg memory_controller_enable_a;
output reg [‘MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_a
;
output reg memory_controller_write_enable_a;
output reg [‘MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in_a;
output reg [1:0] memory_controller_size_a;