throughput this reduces the time taken to get into the |
The structure of the compensator algorithm plays an important |
compensator algorithm by 114ns. This is yet another way to |
role in the time it takes to update the control output variable. |
reduce the total latency in the control loop software. See Figure 4 |
With the alternate working registers, the algorithm can be written |
for details on ADC early interrupt. |
in such a way that the only required computations before |
Another ADC module feature is the inclusion of multiple digital |
updating the control output is to multiply the current error with |
comparators that can be configured to give an interrupt when the |
coefficient B0 and to add that to the accumulated output from |
converted analog result is outside( or within) a given set of limits. |
the previous cycle. Of course the backward normalization and |
This may not seem like a feature that directly impacts the |
clamping is still there but this will significantly reduce the control |
sampling frequency, but it most definitely can. Fewer MIPS are |
output write back time without requiring a dedicated |
consumed when software is offloaded from the CPU and only |
accumulator. Figure 5 shows an example of how the compensator |
executed in a fault condition. This means that we may be able to |
algorithm can be arranged to achieve the quickest update time. |
increase the sampling rate of the control loop. This is highly |
The control output write back time can now occur in less than |
software dependent and not all applications may be able to take |
300ns upon entering the compensator algorithm. It will become |
advantage of this new feature. However, it can reduce the CPU |
clear how this is useful in the following sections. |
work load when it comes to examples like input voltage and |
Now let us consider the impact of all these different features on |
temperature monitoring. |
phase erosion. In voltage mode control and average current mode |
To reduce the time from ADC trigger to control output write back |
control systems, it is possible to sample the output capacitor |
even further the PWM ISR could be used instead of the ADC |
voltage or inductor current at 50 % of the off-time. Most common |
interrupt service routine( ISR) and the ADC early interrupt |
approach is to sample at 50 % on-time to allow enough time to |
feature. In a general use case, the PWM triggers the ADC to start |
process the control algorithm before the start of the next PWM |
conversion but now it will also generate its own interrupt event at |
cycle. With all the features mentioned above it is easily possible |
the same time. With the compensator algorithm placed inside the |
to sample the control feedback signals during the off-time and |
PWM ISR, the software will start executing the compensator |
write back to control output before the start of the next PWM |
algorithm before the current feedback data is available from the |
cycle. Figure 6 shows the estimated duty cycle limits for an |
ADC. There is roughly 143ns between software execution and |
example implementation across switching frequencies while |
completion of the ADC conversion. This means there needs to be |
Figure 7 illustrates a timing diagram of 50 % off-time. The increase |
a minimum of 10 instructions placed before reading the ADC |
in phase margin is dependent on duty cycle but if averaged at |
result buffer when the microcontroller is operating at maximum |
50 % duty cycle the phase erosion drops by half compared to the |
device frequency. If the compensator algorithm is structured in |
50 % on-time measurement. |
such a way that this technique can be used, it will reduce the time | |
taken to get into the compensator routine by 45 %. See Figure 4 | |
for an early interrupt timing example with PWM interrupt service | |
routine. It is important to note that this method should only be | |
applied with the predictable timing of the dedicated SAR cores. | |