ELE Times March 2017 ELE Times | Page 39

PLAY
50 % off-time implementations.
6 for minimum on-time as a percent of the switching period
50 % Off-time
Immediate Updates
Disabled
50 % Off-time
Immediate Updates
Enabled
Write back must happen before start of PWM cycle
Immediate updates enabled allows write back to happen after start of cycle and still apply to falling edge
across different switching frequencies. For example, if will take a boost PFC switching at 100kHz, the minimum on-time requirement would be slightly less than 10 % of the period. As the minimum duty cycle occurs at the peak of the AC line voltage, at nominal 220V input voltage, the duty cycle requirement is around 22 % leaving ample headroom for the immediate update to occur with large variations in the control output. As input voltage increases further, the immediate update will start to look like the end of cycle update and there will be a reduction in phase margin. However, this will occur outside of the nominal conditions. Figure 7 also shows the timing diagram for a 50 % ontime trigger use case as compared against the 50 % on-time trigger schemes.
50 % On-time Immediate Updates Enabled
Write back should happen well before falling edge to account for x % change between cycles
An example was carried out using a synchronous buck converter in which all of the techniques discussed in this article where incorporated. The results showed that the sampling rate increased from every other PWM cycle( 175kHz) to every PWM cycle( 350kHz) without requiring more MIPS, the compensator was written for quick write back to the control output variable, the PWM interrupt was generated for processing the control
Figure 7: 50 % On / Off-time trigger timing diagram
The best case for reducing phase margin erosion is to sample the
control feedback signal at 50 % on-time while ensuring that the
loop, and 50 % on-time with immediate updates was enabled.
new control output is applied to the trailing edge of current PWM
What was observed was an increase in phase margin of roughly
cycle. This implies that the active edge of the PWM duty cycle is
16 degrees. The loop gain performance started out to be
being updated based on the output of the compensator that was
marginally stable with only 46 degrees of phase margin and
just called in the same PWM cycle. This would give the best phase
ended up being very close to an analog counterpart at 62
margin possible in a digital system. One should note that this is
degrees. The techniques for reducing phase erosion in this paper
the optimum use case but cannot be implemented in all
are not a cure-all; however they are applicable to a wide range of
applications due to limitations with minimum on-time. See Figure
designs and will provide some degree of loop gain enhancements.
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ELE Times | 39 | March, 2017