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Figure 2 : 3P3Z Linear Difference Equation
In most PSUs that employ a digital compensator , the control of the power stage is typically governed by a simple LDE . While the LDE approach is well known and commonly used , digital implementations are conducive to implementing nonlinear control algorithms . Nonlinear techniques , however , are beyond the scope of this article .
The size of the LDE depends on the order of the compensator and the method used to transform the continuous frequency function to a discrete frequency function ( forward / backward Euler , bi- linear Transform , etc .). Simply put , the LDE is a mathematical expression that uses linear combinations of the control errors and previous control outputs to produce the current control output . See Figure 2 for an example of a 3P3Z linear difference equation .
Let ’ s consider the impact of the alternate working registers on MIPS consumption for high frequency control loops . A compensator algorithm that may have been called every other switching cycle on the dsPIC33FJ devices may now be called every switching cycle and would still utilize the same percentage of MIPS . The phase erosion due to the sampling process was given in Figure 1 . The amount of phase degradation depends on the crossover frequency and sampling frequency . Therefore if the sampling rate is doubled , the phase degradation is reduced by half . This means that the phase erosion went from a 29 % reduction due to device operating speeds to a 50 % reduction when including the use of the alternate working registers .
To illustrate the reduction in phase erosion due to sampling frequency , consider a system with a 175kHz sampling frequency and 10kHz bandwidth , the phase erosion is calculated as roughly 10 degrees . The same system with 350kHz sampling frequency would only have 5 degrees of phase erosion . This additional phase margin can be achieved with the dsPIC33EP device while utilizing the same percentage of MIPS as compared to the dsPIC33FJ devices .
It can be seen that for the 3P3Z compensator there are seven multiplications and additions that need to occur in order to determine the desired control output . This type of arithmetic is well suited for the architecture of the dsPIC33 devices . These instructions can be processed in seven single cycle instructions using the multiply and accumulate ( MAC ) instruction . However there is going to be additional software overhead that includes : push / pop working registers , loading data in / out of working registers , resetting arrays , and clamping / scaling the control output . This overhead can potentially impact the control loop improved loop gain performance . execution rate which leads to reduced phase margins .
It has been shown that higher sampling frequencies can be obtained with the use of alternate working registers and faster operating speeds of the dsPIC33EP devices leading to reduced phase erosion . Next , let ’ s discuss other device specific peripherals and techniques that can improve phase margin leading to
The dsPIC33EP ‘ GS ’ family of devices include a new 12-bit ADC |
As shown earlier , with the increased MIPS the execution time for |
that incorporates multiple Successive Approximation Register |
the control loop has dropped quite a bit . However , this can be |
( SAR ) cores . The device is capable of sampling multiple analog |
improved even further on the new dsPIC33EP ‘ GS ’ devices with |
inputs simultaneously and having dedicated 12-bit results |
the addition of alternate working registers . These devices |
available in less than 300ns . The dedicated SAR cores are |
incorporate two additional banks of 15 working registers that can |
continuously tracking the input signal which means there is zero |
be made persistent . This means data such as clamp limits , scaling |
sampling time required . When the ADC sees a trigger event it will |
factors , pointers to coefficients , etc . can be preloaded into |
automatically start the conversion process . Remembering that the |
appropriate alternate working registers at the device initialization |
sampling / conversion time is seen as a delay in the control loop , it |
stage . These register banks can then be associated to a given |
will minimize the overall sampling / conversion latency will help |
interrupt priority level which only the control loop software |
with phase margin erosion . |
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would have access to . This will then eliminate the need to push / pop working registers onto the stack and will reduce the overhead of getting data into
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One unique feature about the ADC is the capability to generate the interrupt before conversion completes . This ADC early interrupt feature , when enabled , helps to reduce the interrupt latency from the time the ADC completes conversion to the start of control loop software ( interrupt ). The maximum selectable |
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& PDCx |
Figure 3 is an example of how |
early interrupt timing is eight ADC clocks ( Tads ). At the fastest |
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ACCAL / misc .
ACCAH / misc .
ACCAU / misc . postScaler postShift
& Struct . Opt
& A / B Coeffs
& Error / Control Hist . minClamp
MaxClamp
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to successfully utilize an alternate working register set using Microchip ’ s hardware accelerated compensator functions . It is important to remember that certain registers are required for particular instructions which impose limitations to where data can be placed . |
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open |
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Figure 3 : Alternate Working Register Example
Figure 4 : ADC Early Interrupt Timing
ELE Times | 37 | March , 2017