VLSI Design ( 8 ) ( 15 9 )
The complete counter is implemented using the ESOP expressions ( 8 ) to ( 15 ) and the resulting reversible circuit is shown in Figure 7 where C is the clock input ; the input L performs the asynchronous load with L = 0 for normal operation and
L = 1for asynchronous load ; and the input determines the count direction with M = 0 for up and M = 1 for down .
M The