8 VLSI Design
the controlled swap gate is 5 . Thus the quantum cost of this section is 10 , and no ancilla inputs are required .
( 4 ) Reset . The reset is achieved using two controlled swap gates controlled by the reset input . In Rthe sequential circuit represented by Figure 4 , the reset state is 00 . During synchronous operation , the clock must be set to C = 1 and the reset must be cleared to R = 0 to maintain the present clock state unchanged and the reset . For must the both falling-edge be cleared triggering to CR = action 00 ,. the The
reset action takes place asynchronously when the clock and
Table 2 : Comparison of reversible realization of the sequential circuit in Figure 6 with replacement design method and direct design method in [ 26 ].
Quantum cost
Ancilla input Replacement design [ 26 ] 96 18 Direct design [ 26 ] 88 9
Present design |
53 |
6 |
% replacement improvement design over [ 26 ] |
44.79 |
66.67 |
% improvement over 39.77 33.33 reset action takes place asynchronously when the clock and % improvement over the reset are both set to CR = 11 . In this case , the constant direct design [ 26 ]
inputs the reset 00 must are transmitted be set to R = to the 0 in state order outputs to maintain . At this the point state ,
outputs unchanged . Again , the duration of the reset value R = 1 must be carefully determined to avoid malfunction
of the sequential circuit . The quantum cost of this section is also 5 times the number of bits in the state of the sequential circuit , since for each bit a controlled swap gate is required and the quantum cost of the controlled swap gate is 5 . This section requires ancilla inputs exactly equal to the number of bits in the state . Thus the quantum cost of this section is 10 and 2 ancilla inputs are required .
( 5 ) Feedback . The feedback of the present state is generated using two CNOT gates used as copying gates and is achieved by setting the target input to be 0 . The quantum cost of this section is exactly equal to the number of the bits in the state of the sequential circuit , since one CNOT gate is required for each bit of the state and the quantum cost of the CNOT gate is 1 . This section requires ancilla inputs exactly equal to the number of bits in the state of the sequential circuit , since for each bit of the state one constant-initialized input is required . The quantum cost of this section is 2 and 2 ancilla inputs are required .
( 6 ) Output Logic . The output z is realized as a function of the
input x and the present state Q0 using ( 6 ). The total quantum cost of the circuit in Figure 6 is 53 and 6 ancilla inputs are required . These values are compared
Table 3 : Truth table representing the next states and the modified next states of a four-bit up counter [ 43 ].
Present state |
Next state |
Modi fiednext state |
Q3Q2Q1Q0 |
Q3
+
+
Q2
Q1
Q0
|
∗
Q3
Q2
∗
∗
Q1
Q0
|
0000 |
0001 |
0001 |
0001 |
0010 |
0011 |
0010 |
0011 |
0001 |
0011 |
0100 |
0111 |
0100 |
0101 |
0001 |
0101 |
0110 |
0011 |
0110 |
0111 |
0001 |
0111 |
1000 |
1111 |
1000 |
1001 |
0001 |
1001 |
1010 |
0011 |
1010 |
1011 |
0001 |
1011 |
1100 |
0111 |
1100 |
1101 |
0001 |
1101 |
1110 |
0011 |
1110 |
1111 |
0001 |
1111 |
0000 |
1111 |
Q1 ∗ = Q0,
1Q 0 , ( 9 )
with those of the replacement design approach in [ 26 ] and |
|
|
the direct design in [ 26 ] in Table 2 . The % improvement over |
Q0 ∗ = 1 . |
( 11 ) |
( 10 ) previous designs is calculated using the formula Previous −
= Present × % Improvement
100 . ( 7 )
Previous
From Table 2 , we see that our new present design technique saves significantly on quantum cost and ancilla inputs as compared to both previous replacement design technique and the direct design technique presented in [ 26 ].
5.2 . Example 2 : 4-Bit Up / Down Counter . In this section ,
we illustrate the application of our technique to the design of a four-bit falling-edge trigged up / down counter with asynchronous load . The truth table representing the next
Similarly , the modified next states of the four-bit down counter are minimized as ESOP expressions as follows :
Q3 ∗ = Q2Q1Q0 , Q2
∗
1
∗
( 12 ) = Q1Q0 , ( 13 )
∗
=
Q0 , ( 14 )
Q0 1 . states and the modified next states of the counter is shown in Table 3 . The modified next states of the four-bit up counter from Table 3 are minimized as ESOP expressions as follows :