10 VLSI Design
L
Modified next state logic
Next state logic trigger Asynchronous load Feedback
M |
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M |
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C
0
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Q3 |
Q3 |
Q3 + |
C
Q3
|
0 |
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|
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Q2 |
0 |
Q2 |
Q2 + |
Q1 |
1 Q0
Q1 +
0 Q1 0 0
Q0 +
0 Q0
L
D0 D1 D2 D3
Figure 7: Reversible realization of the four-bit falling-edge triggered up / down counter with asynchronous load [ 43 ].
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design is similar to that of the previous example( Example
1).
The operation of the circuit is discussed below.
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Table 4: Comparison of reversible realization of the four-bit fallingedge triggered up / down counter with asynchronous load with that in [ 26 ]( including data previously presented in [ 43 ]). |
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( 1)
C = 1 and L = 1: Asynchronous Load. The data inputs D3,
D2, D1, and D0 are loaded to the present state outputs Q3,
Q2,
Q1, and Q0( respectively) through the controlled swap gates that make up the Asynchronous Load section of the circuit. After loading the input data, we set L = 0 to maintain
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Design of [ 26 ]
Present design
% improvement over
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Quantum cost
94
74
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Ancilla input
8
8
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the present state output. design of [ 26 ]
21.28 0
( 2) M = 0: Modified Next State Generation for Up Count. The six M-controlled CNOT gates of the Modified Next targets and the fed-back state values Q3, Q2, Q1, and Q0
State Logic section will not modify the logic values of their
remain unchanged. These fed-back state values are used in the Modified Next State Logic section to generate modified next states Q3 ∗, Q2 ∗ Q1, ∗, and( see( 8) to( 11)).
Q The first three CNOT gates controlled by M
0 ∗ complement
compared with that in [ 26 ] as shown in Table 4. From the table, we see that the present design saves quantum cost with
no increase of ancilla inputs.
5.3. Example 3: 4-Bit Universal Register. In this section, we illustrate the synthesis process for a four-bit falling-edge triggered universal register. The truth table representing the wh Q3 ∗ere D∗R is the serial data input. The modified next states
∗ ∗
the fed-back present states Q3, Q2, Q1, and Q0. These
, Q2, Q1, and Q0 are minimized as ESOP expressions
( 3) M = 1: Modified Next State Generation for Down Count. Logic complemented section to values generate are modified used in next the states Modified
Q3
Next State ∗, Q2 ∗, Q1 ∗,
∗
and Q0( see( 12) to( 15)). The last three CNOT gates of
the Modified Next State Logic section restore the fed-back
next states and the modified next states is shown in Table 5, as follows:
Q3 ∗ = DR ⊕ Q3,
Q2
∗
∗
( 16)
= Q3 ⊕ Q2,( 17)