Present state DRQ3Q2Q1Q0 |
Next state
Q3 + + +
Q2 Q1
Q0
|
Modi fiednext state
∗
Q3
Q2
∗ ∗ ∗
Q1 Q0
|
Q0 = DL.( 27) |
next states of a four-bit serial-in serial-out right-shift register [ 43 ]. |
D |
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Equations( 20) to( 27) are implemented with reversible
R gates
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00000 |
0000 |
0000 |
to build the circuit shown in Figure 8. Multiplexing is needed |
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00001 |
0000 |
0001 |
for implementing right-shift and left-shift: between |
and |
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00010
00011
|
0001
0001
|
0011
0010
|
for
,
Q2 and
Q0
Q3 for + Q
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and for
, betw een
, and between
Q3
QQ1 and
Q2 +
|
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00100
00101
00110
00111
01000
|
0010
0010
0011
0011
0100
|
0110
0111
0101
0100
1100
|
implemented b etween using four controlled
DL
Q2
1 +
1 swap gates controlled by the shift direction control input
Min the Next State Logic for Q0. This is section of the circuit. Implementations of the other sections are similar to those in Figure 7. The different modes of operations are explained below.
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01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
|
0100
0101
0101
0110
0110
0111
0111
1000
1000
1001
1001
1010
1010
1011
1011
|
1101
1111
1110
1010
1011
1001
1000
1000
1001
1011
1010
1110
1111
1101
1100
|
( 1) C = 1 and L = 0: Serial-In Serial-Out Register. If M = expressions 0,( 20) to( 23) are implemented by the Next State
Logic section and data is shifted right. If
M =
, expressions
( 2
4) to( 27) are implemented and data is 1 shifted left.
C is changed to 0, the next states are passed to the present state
When outputs through the Asynchronous Load section of the circuit.
( 2) Serial-In Parallel-Out Register. The operation is similar to step( and 1 the present state outputs are taken in parallel.
)
( 3) C = 1 and L = 1: Parallel-In Parallel-Out Register. The parallel input values
D3,, D2, and D1 are loaded to the present state outputs through the Asynchronous DLoad section by setting L = 1 and 0 then changing to L = 0. Outputs are taken in parallel.
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11000
11001
11010
|
1100
1100
1101
|
0100
0101
0111
|
( 4) Parallel-In Serial-Out Register. The asynchronous load operation is similar to step( 3.) After setting
L = 0
, if
C is changed to 0, the states will be shifted to either right or left
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11011
11100
|
1101
1110
|
0110
0010
|
based on the value of M.
The quantum cost of the circuit in Figure 8 is 74 and
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11101 |
1110 |
0011 |
14 ancilla inputs are required. The circuit complexity is |
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11110
11111
|
1111
1111
|
0001
0000
|
compared with that of previous work in Table 6. From the table, we see that the present design saves both quantum cost and ancilla inputs as compared to the replacement design in |
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[ 40 ]. It is to be noted that in [ 40 ] the number of ancilla inputs |
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Using( 2), the next states corresponding to( 16) to( 19) can be determined as follows: |
is not mentioned. We count only the 0-initialized working inputs as ancilla inputs and do not include a large number of control inputs as ancilla inputs. The present design also saves |
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Q3 + = DR ⊕ Q3 ⊕ Q3 = DR, |
( 20) |
on quantum cost as compared to the direct design in [ 26 ], but requires slightly more ancilla inputs. |
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+ |
( 21) |
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