16
VLSI Design
Modified next state logic
Next state logic
R
C
x
1 Q1 ∗ Q1 +
Q1
Q0 ∗ Q1
Q0 +
1 Q0 Q0
Falling-edge trigger
Asynchronous reset
Feedback
Output logic
R
C
z
Q1
Q0
0
Q1
0
Q0
0
0
L MN = 0
L ４， = 0
L F = 0
L O = 0
Figure 10: Online testable design of reversible sequential circuit of Figure 6 for single line fault testing.
inputs as compared to the replacement design in [40]. The
register design also saves 33.93% in quantum cost with a
16.67% increase in ancilla inputs over that in [26].
We also present an online testable design for sequen- tial
reversible circuits for detecting single line faults. The
technique presented in [44] is used for testing Toffoli-
cascade portions of the circuit. For testing sections of the
circuit built from controlled swap gates we propose a new
testing technique. The testable design can simultaneously
detect multiple single line faults in different sections of the
circuit. As shown in Figure 10 the online testable version of
Figure 6 requires only 96.23% quantum cost overhead.
Furthermore, tests of several benchmarks indicate that as the
circuit complexity grows the percentage overhead required
for testability decreases.
Future work includes automation of the mapping process
and consideration of online testability for all three fault
models.
Disclosure
The first author did most of his work at the University of
Lethbridge while on sabbatical from East West University,
Dhaka, Bangladesh.
Conflicts of Interest
The authors declare that there are no conflicts of interest
regarding the publication of this paper.
Acknowledgments
The second author was supported by a grant from Canada’s
National Science and Engineering Research Council
(NSERC) while pursuing this research.
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