VLSI Design
15
Table 7: Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks, both before and after adding
gates for testability.
Filename
bbara
bbsse
bbtas
beecount
cse
dk14
dk512
donfile
ex1
ex2
ex3
ex4
ex5
ex7
keyb
lion9
lion
planet1
planet
s1a
s1
s8
sand
shiftreg
sse
styr
tav
tbk
train11
train4
Inputs
4
7
2
3
7
3
3
2
9
2
2
6
2
2
7
2
2
7
7
8
8
4
11
1
7
9
4
6
2
2
Outputs
2
7
2
4
7
5
5
1
19
2
2
9
2
2
2
1
1
19
19
6
6
1
9
1
7
10
4
3
1
1
States
10
16
6
7
16
7
4
24
20
19
10
14
9
10
19
9
4
48
48
20
20
5
32
8
16
30
4
32
11
4
Total before testability
GC
QC
Number of lines
46
1096
14
99
1361
22
21
203
10
53
577
13
137
2922
22
104
973
14
58
491
12
67
877
13
355
3979
38
97
1924
14
51
715
12
74
618
23
43
631
12
48
680
12
110
4946
19
34
505
11
15
79
7
646
4763
38
646
4763
38
97
3668
24
197
3864
24
36
1036
11
288
4941
30
17
29
8
98
1378
22
338
6553
29
23
403
12
110
3621
19
47
742
11
18
103
7
The total overhead quantum cost of the circuit in Figure 10 is
20+ 16+ 1 0 + 5 = 51. The quantum cost of the original circuit
in Figure 6 is 53. Therefore, the quantum cost overhead of the
testable circuit is only 96.23%.
7. Experimental Results
The process for designing the sequential reversible circuit
and adding the gates for testability was applied to several
sequential benchmarks from the MCNC suite of benchmarks
[48]. As shown in Table 7, the additional circuitry required
for making the sequential reversible circuit testable adds an
average of 30% overhead, in terms of quantum cost. The
highest percentage overhead occurs for the smallest circuits;
this is a result of needing to copy the input and output lines
several times. In larger circuits, the percentage overhead is
significantly lower.
GC
116
185
73
111
223
164
104
145
483
177
117
162
109
114
200
98
51
784
784
197
297
90
400
65
184
448
69
200
111
54
QC
1242
1629
285
729
3266
1229
645
1069
4797
2178
867
838
767
826
5236
621
137
6169
6169
3942
4338
1150
5609
99
1644
7319
487
3911
884
167
Total after testability
Number of lines
% increase in QC
18
13.30
26
19.70
14
40.40
17
26.30
26
11.80
18
26.30
16
31.40
17
21.90
42
20.60
18
13.20
16
21.30
27
35.60
16
21.60
16
21.50
23
5.90
15
23.00
11
73.40
42
29.50
42
29.50
28
7.50
28
12.30
15
11.00
34
13.50
12
241.40
26
19.30
33
11.70
16
20.80
23
8.00
15
19.10
11
62.10
8. Conclusion
In this work, an improved synthesis approach for sequential
reversible circuits is presented. Three design examples are
demonstrated, including an arbitrary sequential circuit with
2-bit states, 1-bit input, and 1-bit output (Figure 4); a four-bit
falling-edge triggered up/down counter with asynchronous
load and a four-bit falling-edge triggered universal register
are shown. We compare the quantum cost and the ancilla
inputs of the three designs with both the replacement design
technique and the direct design technique reported in [26].
The new design of the sequential circuit in Figure 4 saves
44.79% and 39.77% in quantum cost and 66.67% and 33.33%
in ancilla inputs as compared to the replacement design and
direct design in [26], respectively. The new counter design
saves 21.28% in quantum cost with the same number of ancilla
inputs as compared to the design in [26]. The new register
design saves 66.36% in quantum cost and 22.22% in ancilla