Tesi Robotica Algoritmi ed architetture per la risoluzione di... | Page 59

3.2. CONVERSIONE C TO HARDWARE: HIGH LEVEL SYNTESIS
(

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clk,
reset,
start,
finish,
return_val
);
input clk;
input reset;
input start;
output wire finish;
output wire [31:0] return_val;
wire memory_controller_waitrequest;
wire memory_controller_enable_a;
wire [‘MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_a;
wire memory_controller_write_enable_a;
wire [‘MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in_a;
wire [1:0] memory_controller_size_a;
wire [‘MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out_a;
wire
wire
wire
wire
wire
wire

memory_controller_enable_b;
[‘MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_b;
memory_controller_write_enable_b;
[‘MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in_b;
[1:0] memory_controller_size_b;
[‘MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out_b;

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assign memory_controller_waitrequest = 0;

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memory_controller memory_controller_inst (
...
);
main main_inst(
...
);

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endmodule
‘timescale 1 ns / 1 ns
module memory_controller
(
...

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