Tesi Robotica Algoritmi ed architetture per la risoluzione di... | Page 58

3.2. CONVERSIONE C TO HARDWARE: HIGH LEVEL SYNTESIS 5 10 15 58 // Generated by LegUp High-Level Synthesis Tool Version 3.0 (http://legup .org) // Compiled: Mon Jan 21 23:17:46 2013 // University of Toronto // For research and academic purposes only. Commercial use is prohibited. // Please send bugs to: [email protected] // Date: Wed Mar 26 18:19:20 2014 //-------------------------------------------------------------------// ‘define MEMORY_CONTROLLER_ADDR_SIZE 32 ‘define MEMORY_CONTROLLER_DATA_SIZE 64 // Number of RAM elements: 5 ‘define MEMORY_CONTROLLER_TAG_SIZE 9 ‘define TAG_NULL ‘MEMORY_CONTROLLER_TAG_SIZE’d0 ‘define TAG_PROCESSOR ‘MEMORY_CONTROLLER_TAG_SIZE’d1 // @.str1 = private unnamed_addr constant [12 x i8] c"homogeneous\00" 20 ‘define TAG_g__str1 ‘MEMORY_CONTROLLER_TAG_SIZE’d2 ‘define TAG_g__str1_a {‘TAG_g__str1, 23’b0} // @.str2 = private unnamed_addr constant [11 x i8] c"structured\00" 25 30 35 ‘define TAG_g__str2 ‘MEMORY_CONTROLLER_TAG_SIZE’d3 ‘define TAG_g__str2_a {‘TAG_g__str2, 23’b0} // @.str3 = private unnamed_addr constant [20 x i8] c"success_homogeneous \00" ‘define TAG_g__str3 ‘MEMORY_CONTROLLER_TAG_SIZE’d4 ‘define TAG_g__str3_a {‘TAG_g__str3, 23’b0} // @.str4 = private unnamed_addr constant [19 x i8] c"success_structured \00" ‘define TAG_g__str4 ‘MEMORY_CONTROLLER_TAG_SIZE’d5 ‘define TAG_g__str4_a {‘TAG_g__str4, 23’b0} // @gimp_image1 = //Immagine non caricata, align 4 ‘define TAG_g_gimp_image1 ‘MEMORY_CONTROLLER_TAG_SIZE’d6 ‘define TAG_g_gimp_image1_a {‘