ELE Times : What is the latest EDA tool |
sequence , called throughput ( 5x faster |
your company is offering focusing on IC |
than the previous generation ), 10X faster |
Design and how is it different from its |
time-to-visibility , or time to debug , 3X |
predecessors ? |
faster compilation time ( with 100 % |
Harry Foster : The latest product launch |
success rate ) and 3X faster virtual cofrom |
Mentor Graphics is for the Veloce |
model bandwidth ( the fastest virtual co- |
Strato emulation platform , Mentor ’ s thirdimprovements |
model solution available ). All of these |
generation emulation platform with a |
in performance are |
capacity roadmap to 15 billion gates . In |
attributed to the new Veloce Strato OS . |
addition to announcing the VeloceStrato |
ELE Times : What is your company doing |
platform , Mentor announced two |
to eliminate the dilemma in terms of cost |
significant products that are part of the |
for design engineers who needs entryplatform |
: the Veloce StratoM high- |
level desktop solutions that are fast to |
capacity emulator , and the Veloce Strato |
pick up but limited in capability ? |
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OS enterprise-level operating system .
Veloce StratoM is the initial piece of hardware for the Veloce Strato emulation platform , and Veloce Strato OS is the centerpiece of the total emulation system as it allows verification teams to take full advantage of the power of the Veloce
StratoM hardware .
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Harry Foster : Concerning cost in general , the EDA industry has done a remarkable job of managing cost to keep up with
Moore ’ s Law . In fact , what is amazing is that the EDA cost per transistor continues to decrease at about 30 percent per year since 1985 . This is essentially the same rate as the decrease in revenue per
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For those who are not familiar with |
transistor , which is another way of stating |
hardware emulation , let ’ s talk about |
Moore ’ s Law . The point is that if the EDA |
howhardware emulation works . A |
cost per transistor didn ’ t decrease at the |
hardware emulator is a high-capacity , |
same rate as the revenue per transistor , |
piece of hardware equipment that is |
then we would not be able to achieve |
designed to verify SoC designs using the |
Moore ’ s Law . |
RTL description of the SoC design . The RTL description is a ‘ software or code ’ version of the design . But when it is compiled on to the emulator ( which is loaded with boards that are populated with chips ) it becomes a hardware version of the design that is resident in the emulator . From that point engineers run ‘ tests ’ on the hardware version of the designto verify that the design works as expected . In addition , they can run firmware , OS boot code and many other ‘ application ’ types of software on the hardware version of the design to verify that the software for the system works in advance of actual silicon availability . An emulation team uses the test results to debug the hardware design and the software that is targeted for the design . |
Obviously , there are a wide variety of EDA tools available today . Generally you will find that FPGA and PCB tools are relatively less expensive than IC design tools , and
PCB and FPGA tools vary greatly as to price point and ease of use . But when you start talking about IC design tools , you have to consider not only the “ cost ” of the tool , but the value of what you are getting for the cost and increased productivity .
Designing ICs , especially for the latest silicon process geometries , is a highly complex set of tasks that have to be performed by highly skilled engineers .
There are many complex tasks and tools that make up the IC design process so they are not inexpensive relative to other forms of software like Microsoft Word or Excel , but the cost is more than worth it if
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Mentor Graphics is a leader in the |
companies are able to deliver a working |
emulation market segment and our newly |
chip to market before competitors and |
released Veloce StratoM is the industry ’ s |
thus maximize profitability . |
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most advanced and scalable emulator . It enables design teams to verify design that are extremely large , in fact , up to 15- billion gates in size . While there are no designs that large today , Mentor projects that designs of this size will be a reality by
2021 . The Veloce StratoM has the industry ’ s fastest compile-runtime-debug
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Nonetheless , we are value sensitive to our customers . As an example , for PCB systems design , Mentor Graphics offers a portfolio that scales based on design and organizational complexity . Small teams need tools that are easy to adopt and use .
Large teams made up of domain specialists need a collaboration
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