Digital Logics DLD Research Article | Page 6

6 VLSI Design
R / L C
Inputs
0 / 1
0 / D
Q
Modifie d next state logic
Inputs
Q ∗
Next state
C
Q +
Inputs
Falling- Output
Q + edge
Reset or Q + asynchronous logic Q + triggering loading
Q logic Q Q Q Feedback Q
Q
R / L C Inputs
Q 0 / D
0
0 / 1 Figure 5 : Model of reversible synthesis of sequential circuit .
Outputs
Next state Falling-edge Asynchronous
R
C
Modified next state logic
logic
trigger
reset
Feedback
logic
R
C
x
1
Q1 +
Q1
z
Q1
1
Q0
Q0 +
Q0
Q0
0 0
0
0 Q0
Q1
Figure 6 : Reversible realization of the sequential circuit described by Figure 4 ( b ).
Table 1 : Truth table representing the next states , the modified next
( 2 )
∗
Next Stat
+
e Logic . The n
∗
ext states are realized as Q1 + = Q1⊕ states , and the output of the sequential circuit from Figure 4 ( b ).
Q1 and Q∗ 0 = Q0∗⊕ Q0 using the generated modified next
xQ1Q0 Q1 + Q0 + Q1 ∗ Q0 ∗ z states Q1 and Q0 and fed-back present states Q1 and Q0 .
000 10 10 1 001 00 01 0 010 01 11 1 011 10 01 0
This requires two CNOT gates , and thus the quantum cost of this section is exactly equal to the number of bits in the state of the sequential circuit , since for each bit a CNOT gate is required and the quantum cost of the CNOT gate is 1 . No ancilla inputs are required .
100
11
11
0
( 3 ) Falling-Edge Trigger . The falling-edge triggering is
101
01
00
1
achieved using two controlled swap gates controlled by the
110
111
01
00
11
11
0
1
clock C
. When the clock
C = 1 and reset ,
R the = fed-back states are 0 passed to the state outputs , maintaining the state outputs unchanged . When the clock is set to
C = 0 and
R = 0
is maintained , then the generated next states are transmitted
to the state outputs . Just after the next states arrive at the state
Equations ( 4 ), ( 5 ), and ( 6 ) are then used to implement the
output and the feedback of the present states arrives at the
state machine from Figure 4 ( b ), resulting in the circuit shown in Figure 6 . Each section of this circuit is explained below .
Falling-Edge Trigger section , the clock must be set to
C = 1 in order to maintain the new present state at the output . Thus ,
( 1 ) Mod ified Next State Logic . The modified next states
∗
Q1 ∗
the changes of the present states occur at the falling-edge of the clock C and the duration of the period of
C = 0 has to be
and Q0 ( see ( 4 ) and ( 5 )) are realized as functions of the input
very carefully determined to avoid malfunction of the circuit .
x
Q1
Q0