Digital Logics DLD Research Article | Page 5

VLSI Design
4.2 of sequential
. Synthesis circuits Model. is Our shown model in Figure for the
5 reversible. First the synthesis modified present state, in the Modified Next State Logic
∗
5
section. The next state is generated using( 2) in
the Next State Logic section. The generated next
state is loaded to the state output as the present
state at the falling-edge of the clock in the
Falling-Edge Trigger section. The asynchronous
reset or load is carried out in the Asynchronous
Load section. The feedback of the present state
is generated in the Feedback section and the
present state is fed back to the Modified Next
State Logic section. Finally, in the Output Logic
section, the output is generated asa function of
the input and the present state. The following
examples explain the use of this model.
5. Design Examples
In this section, we use three examples to illustrate the design model discussed in Section 4.2.
5.1. Example 1: Sequential Circuit from F igure 4( b). The truth
+ +
circuit in Figure 4( b) is shown in Table 1. The modified next states and the output are minimized as ESOP expressions as follows: table representing the next states( Q1 Q0), the modified
∗
next states( Q1 Q0), and the output( z) of the sequential
∗ ∗
∗
( Q1 Q0)( z)
Q1 ∗ = Q0 ⊕ xQ1Q0,( 4)
Q0 ∗ = 1 ⊕ xQ1 ⊕ Q1Q0,( 5) z = Q0 ⊕ x.( 6)