Tesi Robotica Algoritmi ed architetture per la risoluzione di... | Page 136

136
s_EXE: if (!finish) Y_D = s_EXE; else Y_D = s_DONE;
935

s_DONE: Y_D = s_DONE;

940

945

end

default: Y_D = 3’bxxx;
endcase

// current state
always @(posedge clk)
begin
if (reset) // synchronous clear
y_Q <= s_WAIT;
else
y_Q <= Y_D;
end

950

955

960

965

970

975

always @(posedge clk)
if (y_Q == s_EXE && finish)
return_val_reg <= return_val;
else if (y_Q == s_DONE)
return_val_reg <= return_val_reg;
else
return_val_reg <= 0;
assign start = (y_Q == s_START);
endmodule
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;