Tesi Robotica Algoritmi ed architetture per la risoluzione di... | Page 115

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memory_controller_enable_a,
memory_controller_enable_b,
memory_controller_write_enable_a,
memory_controller_write_enable_b,
memory_controller_in_a,
memory_controller_in_b,
memory_controller_size_a,
memory_controller_size_b,
memory_controller_waitrequest,
memory_controller_out_reg_a,
memory_controller_out_reg_b
);

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input clk;
input memory_controller_waitrequest;
input [‘MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_a;
input memory_controller_enable_a;
input memory_controller_write_enable_a;
input [64-1:0] memory_controller_in_a;
input [1:0] memory_controller_size_a;
output reg [64-1:0] memory_controller_out_reg_a;
reg [64-1:0] memory_controller_out_prev_a;
reg [64-1:0] memory_controller_out_a;
reg memory_controller_enable_reg_a;
input [‘MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_b;
input memory_controller_enable_b;
input memory_controller_write_enable_b;
input [64-1:0] memory_controller_in_b;
input [1:0] memory_controller_size_b;
output reg [64-1:0] memory_controller_out_reg_b;
reg [64-1:0] memory_controller_out_prev_b;
reg [64-1:0] memory_controller_out_b;
reg memory_controller_enable_reg_b;

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reg
reg
reg
reg
reg

[3:0] _str1_address_a;
[3:0] _str1_address_b;
_str1_write_enable_a;
_str1_write_enable_b;
[7:0] _str1_in_a;