Tesi Robotica Algoritmi ed architetture per la risoluzione di... | Page 111

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OPT_FLAGS = -load=$(LIB_DIR)LLVMLegUp.so \
-legup-config=$(LEVEL)/../hwtest/$(FAMILY).tcl \
-legup-config=$(LEVEL)/legup.tcl \
$(LOCAL_CONFIG)
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# path to llvm-ar libraries, such as LLVM intrinsics
AR_DIR = $(LEVEL)/lib/llvm

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# include area information and global settings
LLC_FLAGS = -legup-config=$(LEVEL)/../hwtest/$(FAMILY).tcl \
-legup-config=$(LEVEL)/legup.tcl \
$(LOCAL_CONFIG)
# name of Verilog file
VFILE = $(NAME).v
# name of Verilog file
VFILE = $(NAME).v

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# create work directory if necessary
ifeq ($(wildcard work),)
VLIB = vsim $(VSIMFLAG) -c -do "vlib work; exit;"
else
VLIB =
endif
# CFLAG optimization level switch
ifeq ($(NO_OPT),1)
CFLAG += -O0
else
CFLAG += -O3
endif
# link time optimization switch
ifeq ($(NO_INLINE),1)
LDFLAG += -disable-inlining -disable-opt
CFLAG += -mllvm -inline-threshold=-100
endif
# targets to make
TARGETS = all watch v p q f tiger tiger_prof tigersim tigersim_prof gprof
emul emulwatch emultest emultrace hierarchy cleantiger clean