My first Magazine Dell laptop schematic diagram | Page 7
4
HOST
HCLKN
HCLKP AG1
AG2 CLK_MCH_BCLK#
CLK_MCH_BCLK
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3 K4
T7
Y5
AC4
K3
T6
AA5
AC5 H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
J7
W8
U3
AB10 H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP# B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3 H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#
HRS0#
HRS1#
HRS2# B4
E6
D6 H_RS#0
H_RS#1
H_RS#2
H_ADSTB#0 4
H_ADSTB#1 4
7
7
8
8
CLK_MCH_BCLK# 13
CLK_MCH_BCLK 13
H_DSTBN#[0..3] 4
H_DSTBP#[0..3] 4
17
17
17
17 DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
17
17
17
17 DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
4
4
4
4
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3 AC35
AE39
AF35
AG39 DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3 AE37
AF41
AG37
AH41 DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3 AC37
AE41
AF37
AG41 DMITXP0
DMITXP1
DMITXP2
DMITXP3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3 AY35
AR1
AW7
AW40 SM_CK0
SM_CK1
SM_CK2
SM_CK3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3 AW35
AT1
AY7
AY40 SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB AU20
AT20
BA29
AY29 SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB# AW13
AW12
AY21
AW21 SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
M_OCDOCMP0
M_OCDOCMP1 AL20
AF10 SM_OCDCOMP0
SM_OCDCOMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3 BA13
BA12
AY20
AU21 SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
2 80.6_0402_1%
2
80.6_0402_1%
SMRCOMPN
SMRCOMPP
V_DDR_MCH_REF
PM_BMBUSY#
17 PM_BMBUSY#
PM_EXTTS#0
7,8 PM_EXTTS#0
PM_EXTTS#1
PM_EXTTS#1
H_THERMTRIP#
4,16 H_THERMTRIP#
NB_PWRGD
15 NB_PWRGD
PLTRST_R#
2
1
R76
100_0402_1%
15,17,22,23,26 PLT_RST#
AV9
AT9
AK1
AK41 SM_VREF0
SM_VREF1
G28
F25
H26
G6
AH33
AH34 PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#
K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26
a
ICH_SYNC#
CALISTOGA_FCBGA1466~D
D_REF_CLKN
D_REF_CLKP
D_REF_SSCLKN
D_REF_SSCLKP
CLK_REQ#
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
CFG4
PAD
CFG5
CFG6
PAD
CFG7
CFG8
PAD
CFG9
CFG10
PAD
CFG11
CFG12
CFG13
CFG14
PAD
CFG15
PAD
CFG16
CFG17
CFG18
CFG19
CFG20
m
o
MCH_CLKSEL0 13
MCH_CLKSEL1 13
MCH_CLKSEL2 13
CFG3
12
T2
12
CFG5
T1
CFG7
12
T4
CFG9
12
T3
CFG11
12
CFG12
12
CFG13
12
T5
T7
CFG16
12
CFG17
12
CFG18
12
CFG19
12
CFG20
12
c
.
s
i t c
SM_RCOMPN
SM_RCOMPP
K28
15 MCH_ICH_SYNC#
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN
m
e
h
c
M_ODT0
M_ODT1
M_ODT2
M_ODT3
s
-
p
to
H_RESET# 4
H_ADS# 4
H_TRDY# 4
H_DPWR# 4
H_DRDY# 4
H_DEFER# 4
H_HITM# 4
H_HIT#
4
H_LOCK# 4
H_BR0#
4
H_BNR# 4
H_BPRI# 4
H_DBSY# 4
H_CPUSLP# 4,16
p
l . a
1
1
R46
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
7
7
8
8
AE35
AF39
AG35
AH39 DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
+1.8V
R47
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
AG33 CLK_MCH_3GPLL
AF33 CLK_MCH_3GPLL#
A27
A26
CLK_MCH_DREFCLK#
CLK_MCH_DREFCLK
C40 MCH_SSCDREFCLK#
D41 MCH_SSCDREFCLK
H32
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18 A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13 T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35
CLKREQA#
D
CLK_MCH_3GPLL 13
CLK_MCH_3GPLL# 13
CLK_MCH_DREFCLK# 13
CLK_MCH_DREFCLK 13
MCH_SSCDREFCLK# 13
MCH_SSCDREFCLK 13
CLKREQA# 13
C
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
B
Layout Note:
Route as short
as possible
R40
+3VS
100_0402_1%
2
M_OCDOCMP0
M_OCDOCMP1
R44
1
PM_EXTTS#0 R67
10K_0402_5%
2
1
@ R65
0_0402_5%
1
2 PM_EXTTS#1 @ R66
10K_0402_5%
2
1
2
100_0402_1%
4
7,8 V_DDR_MCH_REF
V_DDR_MCH_REF
+1.8V
H_SWNG1
1
2
H_SWNG0
1
w
5
+VCCP
w
w
H_VREF
17
17
17
17 DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
H_RS#[0..2] 4
+VCCP
7
7
8
8
H_ADSTB#0
H_ADSTB#1
B9
C13
+VCCP
2
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
7
7
8
8
H_REQ#[0..4] 4
HADSTB#0
HADSTB#1
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.
1
17
17
17
17
7
7
8
8
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
CALISTOGA_FCBGA1466~D
A
U23B
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
D8
G8
B8
F8
A8
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HVREF0
HVREF1
HXRCOMP
HXSCOMP
HYRCOMP
HY SCOMP
HXSWING
HYSWING
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
J13
H_VREF
K13
H_XRCOMP E1
H_XSCOMP E2
H_YRCOMP Y1
H_YSCOMP U1
H_SWNG0
E4
H_SWNG1 W1
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
+VCCP
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
1
Description at page13.
C
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
2
U23A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
D
B
3
H_A#[3..31] 4
H_D#[0..63]
5
4
DPRSLPVR 17,37
Stuff R286 & R281 for A1 Calistoga
A