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J. Eur. Opt. Society-Rapid Publ. 22, 56( 2026)
Fig. 1. a) Optical micrograph of the fabricated Si 3 N 4 PIC, showing different functional regions: WG cutback structures( purple), bend and bend-shift loss structures( cyan), EBL – OL taper structures( yellow), grating coupler( green) and splitter test structures( orange). b) Targeted multilayer stack. From bottom to top: Si substrate, SiO 2 BOX( L-1), Si 3 N 4 WG-GC( L-2) and WG for light incoupling layers( L-4) separated by a 1.25 lm thick SiO 2 buffer layer( L-3). Above these, an additional SiO 2 buffer layer is followed by a gold ground plane, 3 lm thick SiO 2 spacer, and a top gold layer used as the electrodes. Holes in the electrodes are covered with an ITO layer. The red cone illustrates the beam emitted by the GC.
respect to the ions quantization axis. Furthermore, TEoptimized operation limits accessible beam geometries. More recently, implementing transverse-magnetic( TM) modes, with the electric field oriented out of plane, have seen increased attention in integrated quantum and precision systems, such as Si 3 N 4 resonator platforms for laser stabilization [ 26 ], and ion trap applications leveraging GCs for polarization gradient cooling [ 27 ].
We report the design, fabrication, and experimental characterization of the performance of a Si 3 N 4 photonic integrated circuit( PIC) consisting of components such as incoupling structures, splitters, bends, taper sections, and GCs, that are key components for scaling trapped-ion based quantum technologies such as quantum computers and clocks to multiple operating zones. As an example, we use a wavelength of 760 nm for applications with trapped Yb + ions [ 28, 29 ]. The Yb + system underpins a wide range of state-of-the-art applications, including precision optical clocks [ 28, 29 ], trapped-ion quantum information processing [ 30, 31 ], and tests of fundamental physics [ 32 – 35 ]. We characterize the PIC with TE and TM modes and discuss how the observed polarization dependence may be leveraged to extend the photonic toolbox for ion trap quantum technology applications by offering additional design flexibility and enabling dual-polarization architectures.
2 TE and TM light guiding
2.1 Chip design and fabrication
The chip layout( Fig. 1a) comprises several functional sections, including WG cutback structures for the characterization of propagation losses, bend and bend-shift test structures, taper test structures, GC studies, and splitter test structures designed to operate at 760 nm. Together, these sections enable a comprehensive evaluation of polarization dependence, coupling efficiency, and loss mechanisms across the PIC. Each section is highlighted in a different color, corresponding to distinct device groups used to characterize optical performance and assess design variations.
The targeted multilayer trap stack comprises both dielectric and metallic layers, as depicted in Figure 1b. Starting from the silicon( Si) substrate, a thermally grown 3 lm thick buried oxide( BOX) silicon dioxide( SiO 2) layer acts as the lower cladding( L-1). The thickness of this bottom oxide layer is chosen to suppress optical leakage into the silicon substrate. On top of this, a 200 nm thick lowpressure chemical vapor deposition( LPCVD) Si 3 N 4 layer( L-2) is deposited. An intermediate 1.25 lm thick low-temperature oxide( LTO) SiO 2 spacer( L-3) separates this layer from a 15 nm thick LPCVD Si 3 N 4 layer( L-4). Owing to its larger optical mode, this thin Si 3 N 4 layer is positioned at the top of the stack to maximize the separation from the silicon substrate and thereby minimize substrate leakage. An additional 3 lm thickLTOSiO 2 layer( L-5) forms the upper cladding of the PIC and is designed to be sufficiently thick to prevent optical leakage of the guided modes into the metallic layers introduced above. The targeted stack is completed by a 100 nm thick gold ground plane( L-6) introduced to provide electrical isolation and shielding, followed by a 3 lmthickSiO 2 buffer layer( L-7). A top gold layer forming the ion trap electrodes completes the envisioned ion trap architecture, with a thin indium tin oxide( ITO) layer included as a transparent conductive material covering holes in the electrodes that could otherwise affect the trapped ion [ 36 ].
For the fabrication of the PIC, a mix-and-match lithography approach was employed. Features larger than 500 nm, such as WGs and splitters, were realized using optical lithography( OL), whereas smaller features, such as incoupling tapers, were patterned with electron-beam lithography( EBL). Consequently, the Si 3 N 4 GCs were fabricated in two sequential lithographic steps, the taper region defined by OL and the grating teeth subsequently patterned by EBL to achieve the required submicrometer periodicity and duty-cycle precision. The Si 3 N 4 layer thickness of 200 nm was chosen as a compromise between compatibility with OL-based waveguide fabrication, GC coupling efficiency, and the minimum feature sizes achievable by EBL.
All photonic designs and simulations presented in this work are carried out with the full target layer stack in mind.