VLSI Design 13
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Falling-edge |
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L |
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Next state logic trigger Asynchronous load Feedback |
L |
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M C
0
DL 0 0 0 0
DR 0
0
0
0
0
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Q3 Q2
Q1 Q0
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Q3 +
Q2 + Q1 +
Q0 +
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M C
Q3
Q2 Q1
Q0
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0 |
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0 0 0 |
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D0 D1 D2 D3 |
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Figure 8: Reversible realization of the four-bit falling-edge triggered universal register [ 43 ]. |
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Table 6: Comparison of reversible realization of the four-bit fallingedge triggered universal register with that of the replacement design in [ 40 ] and the direct design in [ 26 ].
Quantum cost
Ancilla input Replacement design [ 40 ] 220 18
6.1. Online Testing of Single Line Fault in Toffoli Circuits. A Toffoli circuit is a cascade of NOT, CNOT, and Toffoli gates. In [ 44 ], a method for online detection of single line fault in Toffoli circuits is presented. The method in [ 44 ] is as follows:
( 1) A 0-initialized parity line L circuit. is added to the given
Direct design [ 26 ] |
112 |
12 |
( 2) Assume that the given circuit has p inputs / outputs. At |
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Present design
% improvement over
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74 |
14 |
the beginning of the circuit, p CNOT gates are added, where the controls of the CNOT gates are the p input |
replacement design [ 40 ] |
66.36 |
22.22 |
where the controls of the CNOT gates are the |
input |
% improvement over |
33.93 |
−16.67 |
line L. |
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direct design [ 26 ]
target, then the missing gate will not produce that inversion and this condition can be treated as a single line fault at that position. Thus online detection of single line faults also detects some missing control and missing gate faults.
lines and the target of all the CNOT gates is the parity
( 3) All CNOT and Toffoli gates of the given circuit are replaced by their corresponding extended versions( EFGs and ETGs, respectively). The second target of all gates is the parity line L.
( 4) The NOT gates in the given circuit are retained. If the number of NOT gates in the given circuit is odd, then an extra NOT gate is added at the end of the parity line L.