Digital logic, an Inverter or NOT gate Digital logic, an Inverter or NOT gate | Page 10

Not Gate using NPN Transistor
We can design a NOT gate by using a NPN transistor as shown in below picture.
The Base (B) of the NPN transistor is connected with the input signal X. we
connect a supply voltage of +5 V to the emitter (E) and the output Z is collected
at the emitter. When the low level voltage 0 V is connected to the input, then
the transistor will be OFF. So no current flows through it. This means the
supply voltage +5 V will be measured at the output port, which is considered as
HIGH state
Similarly, when the high level voltage +5 V is connected to the input, then the
transistor will be ON. So the total supply current will be drawn by transistor.
This means the no voltage is measured at the output port, which is considered
as LOW state.
At this situation the output voltage is measured as +5 V, which will be
considered as HIGH logic level. The transistor designed NOT gate is shown
below.